Design of an Efficient Parallel Comparator Architecture for Low Power Delay Product
Mangal Deep Gupta, Rajeev Kumar Chauhan
DOI: 10.15598/aeee.v19i2.4101
Abstract
A binary comparator architecture is proposed in this work for static logic to achieve both low-power and high-performance operations. It also presents a detailed timing performance and power analysis of various state-of-the-art comparator designs. The main advantages of this design are its high speed and power efficiency maintained over a wide range of operands size, which is useful at low-input data activity environments. The proposed circuit design uses minimum fan-in and fan-out logic gates for achieving high speed and low power dissipation. Utilizing a 2-bit binary comparator circuit with minimum fan-in and fan-out of logic gates (NAND-NOR), the architecture of a parallel binary comparator is proposed for higher input operands by using a low radix multiplexer and priority encoder. Further, to decrease the size of the multiplexer and priority encoder by two times, a general architecture is also proposed by using a 4-bit binary comparator to reduce its complexity. The proposed circuits are optimized in terms of the power consumption and delay, which are due to low load capacitance, low leakages, and reduced dynamic power dissipation. Each of the proposed circuits has its own merits in terms of speed, power consumption, Power-Delay Product (PDP). Its synthesis is done on 180 nm as well as 90 nm CMOS technology using the Cadence tool. The physical layout of the proposed architecture using a 90 nm CMOS process (GPDK process) is also obtained.