Reducing the Source Resistance by Increasing the Gate Effect on Substrate for Future Terahertz HEMT Device
Soufiane Derrouiche
DOI: 10.15598/aeee.v19i4.3820
Abstract
In this paper, we present the dependence of source resistance sensibility on the gate bias effect in a High Electron Mobility Transistor (HEMT) using the Drift-Diffus (D-D) model with the SILVACO Technology Computer-Aided Design (TCAD) tool. The obtained results show that the increases of gate bias effect on substrate lead to decreasing the source resistance of the simulated device. The reported increase in the effect of gate induces the increases of transferred holes concentration towards the source region and which induce the decreases of source resistance. The decrease of source resistance can also be made by reducing the buffer thickness which leads to an increase in the gate effect on the substrate. The source resistance value is influenced by the Drain-Induced Barrier Lowering (DIBL) effect where the rate of decreasing the source resistance will be decreasing consequently to increase the drain bias. The reduction of the source resistance induces the increase of device sensibility for lows values of current.