A Novel and Fast Hardware Implementation for Golay Code Encoder
Morteza Nazeri, Abdalhossein Rezai
DOI: 10.15598/aeee.v16i4.2735
Abstract
The Error Correction Code (ECC) is utilized to reduce the probability of error in digital systems. The binary Golay code is an ECC that can correct any combination of three or fewer random errors over a block of 23 digits. This code can be extended by appending a parity check bit to each codeword. There are several algorithms for constructing of Golay code, but more of them are not comfortable for hardware implementation. In this paper, an efficient hardware architecture is presented for the encoder of both binary Golay code and extended Golay code based on CRC. The proposed Golay code encoder is constructed of three units, which are designed carefully: data path, control unit and conversion unit. The proposed architecture is implemented on FPGA using Xilinx ISE 14.2. The implementation results demonstrate that low latency, high throughput, low area and less complexity are the advantages of this architecture compared to previous architectures. Thus, this hardware module can be used for high-speed digital systems.