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University of Brest, France

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National Taiwan University of Science and Technology, Taiwan, Province of China

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UPC Broadband Slovakia, Slovakia

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University of Zilina, Slovakia

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Brno University of Technology, Czech Republic

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Brno University of Technology, Czech Republic

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Ankara University, Turkey

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Institute of Medical Technology and Equipment, Poland

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VSB - Technical University of Ostrava, Czech Republic

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Academy of Sciences of the Czech Republic, Czech Republic

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University of Defence, Czech Republic

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Wroclaw University of Science and Technology, Poland

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Technical University of Radom, Poland

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Technical University of Kosice, Slovakia

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University of Economics in Katowice, Katowice, Poland

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Honeywell International, Czech Republic

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Brno University of Technology, Czech Republic

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Delhi Technological University, India

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Shantou University, China

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VSB - Technical University of Ostrava, Czech Republic

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The University of Edinburgh, United Kingdom

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Tomas Bata University in Zlin, Czech Republic

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University of Zilina, Slovakia

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University of Defence, Czech Republic

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Technical University of Cluj Napoca, Romania

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National Research University "MPEI", Russian Federation

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Guanajuato University, Mexico

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University of Pardubice, Czech Republic

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University of West Bohemia in Plzen, Czech Republic

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Technical University of Cluj Napoca, Romania

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Warsaw University of Technology, Poland

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Isfahan University of Technology, Iran, Islamic Republic Of

Mauro Tropea
DIMES Department of University of Calabria, Italy

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Academy of Sciences of the Czech Republic, Czech Republic

Jiri Vodrazka
Czech Technical University in Prague, Czech Republic

Miroslav Voznak
VSB - Technical University of Ostrava, Czech Republic

He Wen
Hunan University, China

Otakar Wilfert
Brno University of Technology, Czech Republic


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Early Area and Power Estimation Model for Rapid System Level Design and Design Space Exploration

Abhishek Narayan Tripathi, Arvind Rajawat

DOI: 10.15598/aeee.v20i1.4229


Abstract

Power and area estimation in the early stage of designing is very critical for a system. This paper presents the neural network-based early area and power estimation model. The flow starts with the training of the neural network model from the selected behavioral level parameters, which imposes to provide accurate estimations. The model accuracy is validated against ITC99 benchmark programs. The run-times are faster than the synthesis run-times. For the ASIC-based designs, the proposed model took 5 seconds, while Synopsys Design Compiler took 5 minutes. In terms of timing, the estimation speed is more than the order of magnitude faster than the conventional synthesis-based approach. The modeling methodology provides a better, accurate, and fast area and power estimations, at an early stage of the Very-Large-Scale Integration (VLSI) design. In addition, the model eliminates the need for synthesis-based exploration and provides the design picking before synthesis.

Keywords


Area estimation; design space exploration; neural network; power estimation; VLSI.

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