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Booth-Encoded Karatsuba: A Novel Hardware-Efficient Multiplier
Riya Jain, Khushbu Pahwa, Neeta Pandey
DOI: 10.15598/aeee.v19i3.4199
Abstract
There is a recent boom being witnessed in emerging areas like IoMT (Internet of Medical Things), Artificial Intelligence for healthcare, and disaster management. These novel research frontiers are critical in terms of hardware and cannot afford to compromise accuracy or reliability. Multiplier, being one of the most heavily used components, becomes crucial in these applications. If optimized, multipliers can impact the overall performance of the system. Thus, in this paper, an attempt has been made to determine the potential of accurate multipliers while meeting minimal hardware requirements. In this paper, we propose a novel Booth-Encoded Karatsuba multiplier and provide its comparison with a Booth-Encoded Wallace tree multiplier. These architectures have been developed using two types of Booth encoding: Radix-4 and Radix-8 for 16-bit, 32-bit and 64-bit multiplications. The algorithm is designed to be parameterizable to different bit widths, thereby offering higher flexibility. The proposed mul- tiplier offers advantage of enhanced performance with significant reduction in hardware while negligibly trad- ing off the Power Delay Product (PDP). It has been observed that the performance of the proposed architecture increases with increasing multiplier size due to significant reduction in hardware and slight increase in PDP. All the architectures have been implemented in Verilog HDL using Xilinx Vivado Design Suite.
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