Novel Ternary Logic Gates Design in Nanoelectronics

doi:10.15598/aeee.v17i3.3156

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Darius Andriukaitis
Kaunas University of Technology, Lithuania

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The University of Sydney, Australia

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Technical University of Cluj Napoca, Romania

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Slovak University of Technology, Slovakia

Khosrow Behbehani
The University of Texas at Arlington, United States

Mohamed El Hachemi Benbouzid
University of Brest, France

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University of Defence, Czech Republic

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Erik Chromy
UPC Broadband Slovakia, Slovakia

Milan Dado
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Petr Drexler
Brno University of Technology, Czech Republic

Eva Gescheidtova
Brno University of Technology, Czech Republic

Ray-Guang Cheng
National Taiwan University of Science and Technology, Taiwan, Province of China

Gokhan Hakki Ilk
Ankara University, Turkey

Janusz Jezewski
Institute of Medical Technology and Equipment, Poland

Rene Kalus
VSB - Technical University of Ostrava, Czech Republic

Ivan Kasik
Academy of Sciences of the Czech Republic, Czech Republic

Jan Kohout
University of Defence, Czech Republic

Ondrej Krejcar
University of Hradec Kralove, Czech Republic

Miroslaw Luft
Technical University of Radom, Poland

Stanislav Marchevsky
Technical University of Kosice, Slovakia

Byung-Seo Kim
Hongik University, Korea

Valeriy Arkhin
Buryat State University, Russia

Rupak Kharel
University of Huddersfield, United Kingdom

Fayaz Hussain
Ton Duc Thang University, Vietnam

Peppino Fazio
Ca’ Foscari University of Venice, Italy

Fazel Mohammadi
University of New Haven, United States of America

Thang Trung Nguyen
Ton Duc Thang University, Vietnam

Le Anh Vu
Ton Duc Thang University, Vietnam

Miroslav Voznak
VSB - Technical University of Ostrava, Czech Republic

Zbigniew Leonowicz
Wroclaw University of Science and Technology, Poland

Wasiu Oyewole Popoola
The University of Edinburgh, United Kingdom

Yuriy S. Shmaliy
Guanajuato University, Mexico

Lorand Szabo
Technical University of Cluj Napoca, Romania

Tran Trung Duy
Posts and Telecommunications Institute of Technology, Ho Chi Minh City, Vietnam

Xingwang Li
Henan Polytechnic University, China

Huynh Van Van
Ton Duc Thang University, Vietnam

Lubos Rejfek
University of Pardubice, Czech Republic

Neeta Pandey
Delhi Technological University, India

Huynh The Thien
Ho Chi Minh City University of Technology and Education, Vietnam

Mauro Tropea
DIMES Department of University of Calabria, Italy

Gaojian Huang
Henan Polytechnic University, China

Nguyen Quang Sang
Ho Chi Minh City University of Transport, Vietnam

Anh-Tu Le
Ho Chi Minh City University of Transport, Vietnam

Phu Tran Tin
Ton Duc Thang University, Vietnam

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Novel Ternary Logic Gates Design in Nanoelectronics

Sajjad Etezadi, Seied Ali Hosseini

DOI: 10.15598/aeee.v17i3.3156

Abstract

In this paper, standard ternary logic gates are initially designed to considerably reduce static power consumption. This study proposes novel ternary gates based on two supply voltages in which the direct current is eliminated and the leakage current is reduced considerably. In addition, ST-OR and ST-AND are generated directly instead of ST-NAND and ST-NOR. The proposed gates have a high noise margin near V_(DD)/4. The simulation results indicated that the power consumption and PDP underwent a~sharp decrease and noise margin showed a considerable increase in comparison to both one supply and two supply based designs in previous works. PDP is improved in the proposed OR, as compared to one supply and two supply based previous works about 83% and 63%, respectively. Also, a memory cell is designed using the proposed STI logic gate, which has a considerably lower static power to store logic ‘1’ and the static noise margin, as compared to other designs.